1. Field of the Invention
This invention relates to a CMOS latch circuit with improved radiation hardening, and more particularly to a hardening circuit element which can be conveniently incorporated into an application specific latch substrate and which allows fast write setup over a wide temperature range.
2. Description of the Prior Art
In space applications, CMOS static random access memories (SRAMs), and other data storage circuits, such as latches, shift registers, and flip flops, are sensitive to state upset when struck by energetic, heavy ions. A reduction in the integrated circuit device dimensions increases the susceptibility of SRAMs, and other logic circuits, to soft errors caused by upset when the diffusion nodes of these circuits are hit by energetic heavy ions, such as iron, krypton or argon. The phenomenon of a logic state change or a soft error produced by a single ion hit is known as a single event upset (SEU). In space applications, as the number and density of memory cells and logic circuits in the data processing systems increases, the SEU error rate is an increasingly serious problem.
FIGS. 1a and 1b respectively are schematic diagrams of a well known prior art CMOS static random access memory (SRAM) cell and a CMOS latch circuit without radiation hardening.
Single event upset (SEU) or soft error can occur in the SRAM cell or latch circuit shown in FIGS. 1a and 1b respectively following a high energy ion strike at the "off" N and P channel drains (node 1 or node 2) in these circuits. When a high energy ion strikes the drain depletion region, it generates electron hole pairs, which are collected as reverse saturation current. Such currents generated in the drain region of the off transistor change the drain node voltage (for example node 1) and the gate voltage of the opposite invertor transistors (T3 and T4). These changes in drain and gate voltages tend to destabilize the logic states of the latch or SRAM cell circuits.
The amount of change in the node voltage depends on the amount of charge deposited by the high energy ion's strike at the off drain region. The magnitude and the duration of the voltage transients are critical and determine whether or not an SEU occurs. The minimum critical charge (QC) that produces an upset depends upon the characteristics of the transistors and the parasitic capacitances.
In the conventional latch circuit shown in FIG. 1b, data is entered from input to the invertor made up by transistors T5 and T6 while clock at the gate of transistor T7 is high. A high input at data node will produce a high voltage (logic) level at the drains of transistors T1 and T2 (node 1). P-channel transistor T1 is on and N-channel transistor T2 is off. A high level at node 1 and at the gates of transistors T3 and T4 produces a low voltage (logic) level at node 2, keeping T3 off and T4 on. The low voltage level at node 2 latches node 1 to high voltage level even when the clock signal at the gate of the T7 has dropped to low voltage level. Now the latch circuit is in a stable state with node 1 at high and node 2 at low voltage levels.
During the clock cycle, when clock is at low voltage level, if a high energy ion strikes node 1, reverse current in the drain of T2 will pull down the node 1 voltage from a high level to possibly below ground level with the T2 drain to substrate junction becoming forwardly biased. A low voltage at node 1 and simultaneously at the gates of T3 and T4, raises the node 2 voltage to high level and this in turn might latch the node 1 to a low voltage level. The latch circuit states having been thusly upset will produce soft logic errors at the latch output nodes Q and -Q. Similarly, a SRAM cell circuit can be written by a high energy ion's strike storing an erroneous data. SEU can also happen due to a strike at node 2.
As shown in FIGS. 2a and 2b, respectively, in the prior art, SEU immunity or hardness of a SRAM cell and a latch circuit is provided by connecting feedback resistors from the drains of one invertor to the gates of the second invertor; namely, RF1 from node 1 to gates of T3 and T4 and RF2 from drains of T3 and T4 to gates of T1 and T2. C1 and C2 represent the interconnection and parasitic capacitances at the transistor gates. Voltage change at node 1 is delayed by the time constant RF1.times.C1 before it appears at the gates of T3 and T4. During this time node 1 voltage starts to recover because the voltage of gates of T1 and T2 has not yet changed, and the circuit stabilizes to its original logic states. Lightly doped polysilicon resistors RF1 and RF2 require a masking and ion implant process step during the wafer fabrication. Resistor values or doping level are selected to achieve a certain level of immunity to SEU phenomenon.
Drawbacks with the feedback resistor solution for SEU are:
1. The polysilicon resistor temperature coefficient is very high, approximately 1% per C. For circuits designed to operate over a wide temperature range (e.g. -55.degree. to 125.degree. C.), the hold time for latch circuit can be very long in order to achieve certain desired level of SEU immunity.
2. In gate array applications, where integrated circuit (IC) devices are fabricated by personalizing partially processed master slice wafers from stock, forming polysilicon resistors is not practical. The polysilicon personalization step is a step very early in the wafer fabrication.